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Preliminary W78E378/W78C378/W78C374 MONITOR CONTROLLER
GENERAL DESCRIPTION
The W78E378, W78C378 and W78C374B are ASIC which is a stand-alone high-performance microcontroller specially designed for monitor control applications. The device integrates the embedded 80C31 microcontroller core, on-chip MTP or Mask ROM, 576 bytes of RAM, and a number of dedicated hardware monitor functions. Additional special function registers are incorporated to control the on-chip peripheral hardware. The chip is used to control the interface signal of other devices in the monitor and to process the video sync signals. Because of the highly integration and Flash cell for program memory, the device can offer users the competitive advantages of low cost and reduced development time.
FEATURES
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80C31 MCU Core Embedded 32K Bytes MTP-ROM (W78E378) 32K Bytes Mask-ROM (W78C378) 16K Bytes Mask-ROM (W78C374B) Total 576 Bytes of On-chip Data RAM - 256 bytes accessed as in the 80C32 - 320 bytes accessed as external data memory via "MOVX @Ri" PWM DACs - Eight 8-bit Static PWM DACs: DAC0-DAC8 - Three 8-bit Dynamic PWM DACs: DAC9-DAC10 Sync Processor - Horizontal & Vertical Polarity Detector - Sync Separator for Composite Sync - 12-bit Horizontal & Vertical Frequency Counter - Programmable Dummy Frequency Generator - Programmable H-clamp Pulse Output - SOA Interrupt - Hsync/2 Output Serial Ports: - DDC1 Port- support DDC1 - SIO1 & SIO2 Ports - each can support DDC2B/2B+/2Bi/2AB (each has 2 slave addresses) Two 16-bit Timer/Counters (8031's Timer0 & Timer1) One External Interrupt Input (8031's INT0 ) One Parabola Interrupt Generator One ADC with 7 Multiplexed Analog Inputs Two 12 mA(min) Output Pins for Driving LEDs 22 Watchdog Timer (2 /Fosc = 0.42s @Fosc = 10 MHz) Power Low Reset Frequency: 10 MHz max. (with the same performance as a normal 8051 that uses 20 MHz) Packaged in 40/32-pin 600 mil DIP & 44-pin PLCC
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
PIN CONFIGURATIONS
40-pin DIP:
W78E378E W78C378E W78C374E
P4.1 P4.0 (HFI) P3.5 (ADC4, T0)* P1.1 (DAC1)* 40-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P4.2 P4.3 P3.6 (ADC5, T1)* P1.2 (DAC2)* P1.3 (DAC3)* P1.4 (DAC4)* P1.5 (DAC5)* P1.6 (DAC6)* P1.7 (DAC7)* P2.0 (DAC8) P2.1 (DAC9) P2.2 (DAC10) P2.3 (Hclamp) P2.4 (ADC0) P2.5 (ADC1) P2.6 (ADC2) P2.7 (ADC3) P3.7 (ADC6)* P4.4 (SCL2)* P4.5 (SDA2)*
32-pin DIP:
W78E378 W78C378 W78C374
P1.0 (DAC0)* P3.4 (VOUT) P3.3 (HOUT) HIN VIN
RESET VDD
VSSA OSCOUT OSCIN P3.2 ( INT0 ) P3.1 (SCL)* P3.0 (SDA)* VSS P4.7 (HFO) P4.6
44-pin PLCC
P 3 . 4 P 1 . 0 P 1 . 1 P 3 . 5 P 4 . 0 P 4 . 1 P 4 . 2 P 4 . 3 P 3 . 6 P 1 . 2 P 1 . 3
P3.3 H IN VIN RESET VDD VDDA VDD VSSA OSCOUT OSCIN P3.2
7 8 9 10 11 12 13 14 15 16 17 1 1 2 890 P 3 . 1
65432144444 43210
W78E378P W78C378P W78C374P
22222 12345 P 4 . 5 P 4 . 4
39 38 37 36 35 34 33 32 31 30 2 2 2 29 678 P 3 . 7 P 2 . 7 P 2 . 6
P1.4 NC P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
PVVPP 3SS44 . SS. . 0 76
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Preliminary W78E378/W78C378/W78C374
PIN DESCRIPTION
PIN NAME RESET I/O I/O DESCRIPTION Chip reset input (active low) input & Internal reset output (generated by WDT or power low) TTL Schmitt trigger input, internal pull-up ~30 K IOL = +12 mA @VOL = 0.45V VDD VSS VSS OSCOUT OSCIN HIN O I I Positive power supply Ground Ground Output from the inverting oscillator amplifier Input to the inverting oscillator amplifier, 10 MHz max. Hsync input TTL Schmitt trigger input , w/o PMOS VIH/VIL = 2.0V/0.8V, V+/ V- = ~1.6V/ 1.1V VIN I Vsync input TTL Schmitt trigger input, w/o PMOS VIH/VIL = 2.0V/0.8V, V+/ V- = ~1.6V/ 1.1V P1.0 (DAC0) P1.1 (DAC1) P1.2 (DAC2) P1.3 (DAC3) P1.4 (DAC4) P1.5 (DAC5) P1.6 (DAC6) P1.7 (DAC7) I/O I/O I/O I/O I/O I/O I/O I/O General purpose I/O, DAC0 special function output Open-drain output, sink current: 15 mA General purpose I/O, DAC1 special function output Open-drain output, sink current: 15 mA General purpose I/O, DAC2 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC3 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC4 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC5 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC6 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC7 special function output Open-drain output, sink current: 4 mA
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Pin Description, Continued
PIN NAME P2.0 (DAC8) P2.1 (DAC9) P2.2 (DAC10) P2.3 (Hclamp) P2.4 (ADC0) P2.5 (ADC1) P2.6 (ADC2) P2.7 (ADC3) P3.0 (SDA)
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
DESCRIPTION General purpose I/O, DAC8 Special Function output Sink/Source current: 4 mA/-100 A (-4 mA for SF output) General purpose I/O, DAC9 Special Function output Sink/Source current: 4 mA/-100 A (-4 mA for SF output) General purpose I/O, DAC10 Special Function output Sink/Source current: 4 mA/-100 A (-4 mA for SF output) General purpose I/O, Hclamp Special Function output Sink/Source current: 4 mA/-100 A (-4 mA for SF output) General purpose I/O, ADC input channel 0 Sink/Source current: 4 mA/-100 A General purpose I/O, ADC input channel 1 Sink/Source current: 4 mA/-100 A General purpose I/O, ADC input channel 2 Sink/Source current: 4 mA/-100 A General purpose I/O, ADC input channel 3 Sink/Source current: 4 mA/-100 A General purpose I/O, DDC port serial data I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/ 0.4 VDD Open-drain output, sink current: 8 mA General purpose I/O, DDC port serial clock I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/ 0.4 VDD Open-drain output, sink current: 8 mA General purpose I/O, INT0 input Sink/Source current: 1 mA/ -100 A General purpose I/O, HOUT special function output Sink/Source current: 4 mA/-100 A (-4 mA for SF output) General purpose I/O, VOUT special function output Sink/Source current: 4 mA/-100 A (-4 mA for SF output) General purpose I/O, ADC input channel 4 Open-drain output, sink current: 4 mA General purpose I/O, ADC input channel 5 Open-drain output, sink current: 4 mA General purpose I/O, ADC input channel 6 Open-drain output, sink current: 4 mA
P3.1 (SCL)
I/O
P3.2 (INT0 ) P3.3 (HOUT) P3.4 (VOUT) P3.5 (ADC4, T0) P3.6 (ADC5, T1) P3.7 (ADC6)
I/O I/O I/O I/O I/O I/O
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Preliminary W78E378/W78C378/W78C374
Pin Description, Continued
PIN NAME P4.0 (HFI) P4.1 P4.2 P4.3 P4.4 (SCL2)
I/O I/O O O O I/O P4.0 Output, HFI Input
DESCRIPTION Sink/Source current: 4 mA/-4 mA P4.1 Output Sink/Source current: 4 mA/-4 mA P4.2 Output Sink/Source current: 4 mA/-4 mA P4.3 Output Sink/Source current: 4 mA/-4 mA P4.4 Output, SIO2 port serial clock I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/0.4 VDD Open-drain output, sink current: 8 mA
P4.5 (SDA2)
I/O
P4.5 Output, SIO2 port serial data I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/0.4 VDD Open-drain output, sink current: 8 mA
P4.6 P4.7 (HFO)
O O
P4.6 Output Sink/Source current: 4 mA/-4 mA P4.7 Output, HFO Output Sink/Source current: 4 mA/-4 mA
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
BLOCK DIAGRAM
VDD
VSS
80C31 Core excluding internal RAM
Note: freq1 = freq2 freq2
CPU
Interrupt Processor Timer 0 Timer 1 INT0 (P3.2)
OSCIN OSCOUT
freq1
Osc. Circuit
T0 (P3.5) T1 (P3.6)
RESET
Reset Circuit
P1, P2, P3 Power Low Detection I/O Port P4
Note: P1, P4.4~P4.5 P3.0~P3.1 & P3.5~P3.7 are open-drain.
Watch Dog Timer VPP (P3.2) Program Memory
SCL (P3.1) SIO1 SDA (P3.0) SCL2 (P4.4) SIO2 SDA2 (P4.5)
Data Memory
RAM: 576 Bytes
HIN, VIN HFI (P4.0) VOUT (P3.4) HOUT (P3.3) Hclamp (P2.3) HFO (P4.7) ADC0 (P2.4) ADC1 (P2.5) ADC2 (P2.6) ADC3 (P2.7) ADC4 (P3.5) ADC5 (P3.6) ADC6 (P3.7) Sync. Processor Static DACs DAC0~7 (P1.0~P1.7)
Dynamic DACs ADC
8-bit Internal Bus
DAC8~10 (P2.0~P2.2)
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Preliminary W78E378/W78C378/W78C374
FUNCTIONAL DESCRIPTION
Address Space
7FFFh (3FFFh)
Internal Program Memory
FFh
Internal RAM 256 Bytes Indirect Addressing "MOV @Ri"
8051SFRs & Serial Ports SFRs Direct Addressing "MOV"
FFh On-Chip Data Memory C0h BFh
64 Bytes External Access "MOVX @Ri" new SFRs External Access External Access "MOVX @Ri"
80h 7Fh
Direct or Indirect Addressing "MOV" or "MOV @Ri"
80h "MOVX @Ri" 7Fh On-Chip Data Memory
128 Bytes
7Fh On-Chip Data Memory
128 Bytes
External Access "MOVX @Ri"
External Access "MOVX @Ri"
0000h
00h
00h
BANK0
00h
BANK1
Program/Data/SFRs Address Space SFRs accessed using 'Direct Addressing' REGISTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A* B* PSW* SP DPL DPH IE* IP* TCON* TMOD TL0 TH0 TL1 TH1 PCON ADDRESS E0h F0h D0h 81h 82h 83h A8h B8h 88h 89h 8Ah 8Ch 8Bh 8Dh 87h BITS 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 POWER ON RESET 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h RESET 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h x0h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
SFRs accessed using 'Direct Addressing', continued
REGISTER 16 17 18 19 20 21 22 23 24 25 26 27 28 28 P1* P2* P3* TMREG* S1CON* S1STA S1DAT S1ADR1 S1ADR2 S2CON* S2STA S2DAT S2ADR1 S2ADR2
ADDRESS 90h A0h B0h C0h D8h D9h DAh DBh DCh E8h E9h EAh EBh ECh
BITS 8 8 8 3 8 8 8 8 8 8 8 8 8 8
POWER ON RESET 00h FFh 1Fh 00h 00h F8h FFh 00h 00h 00h F8h FFh 00h 00h
RESET 00h FFh 1Fh xxh 00h F8h FFh 00h 00h 00h F8h FFh 00h 00h
R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W
Notes: 1. The SFRs marked with an asterisk (*) are both bit- and byte-addressable. 2. Port 1 and P3.5-P3.7 outputs low during & after reset. 3. "x" means no reset action. 4. The SFRs in the shaded region are new-defined.
* Modified PCON BIT 0 1 2 3 4 5 6 7 NAME ADCS2 PD GF0 GF1 TEST0 TEST1 ADCcal CPUhalt ADC channel Select bit 2 Power Down bit General purpose flag bit General purpose flag bit Test purpose flag bit Test purpose flag bit Set 0/1 to select 1.0V/3.0V for ADC calibration Set to let CPU halt when the chip runs internally FUNCTION
* TMREG: Test Mode Register BIT 0 1 2 NAME TM1 TM2 TM3 Test Mode1 Test Mode2 Test Mode3 FUNCTION
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Preliminary W78E378/W78C378/W78C374
SFRs accessed using 'MOVX @Ri' REGISTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 CTRL1 CTRL2 P1SF P2SF P3SF PARAL PARAH HFCOUNTL HFCOUNTH VFCOUNTL VFCOUNTH WDTCLR SOARL SOARH SOACLR INTMSK INTVECT INTCLR DDC1 ADC DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 DAC10 P4 CTRL3 ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BITS 8 8 8 8 8 8 5 8 8 8 8 8/6 8/6 6 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 POWER ON RESET 00h 00h 00h 00h 00h 00h 00h x x x x x x x x 00h 00h x x x 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh 00h RESET 00h 00h xxh xxh 00h 00h 00h x x x x x x x x 00h 00h x x x x x x x x x x x x x x FFh 00h R/W TYPE W W W W W R/W R/W R R R R W R/W R/W W R/W R W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W
Note: "x" means no reset action.
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
* CTRL1: Control Register 1 (Write Only) BIT 0 NAME ADCSTRT FUNCTION A-to-D Conversion START control Set by S/W to start conversion. Cleared by H/W while conversion completed (read SOARH.6 to check). ADC channel Select bit 0 ADC channel Select bit 1 Enable DDC1 H-Clamp Edge Select 0: Select leading edge of restored Hsync 1: Select trailing edge of restored Hsync H-Clamp Width Select bit Dummy signal Enable Vsync Separator Disable, 0: Enable, 1: Disable
1 2 3 4
ADCS0 ADCS1 ENDDC1 HCES
5 6 7
HCWS DUMMYEN VSDIS
* CTRL2: Control Register 2 (Write Only) BIT 0 1 2 3 4 5 6 7 NAME HSPS VSPS HDUMS0 VDUMS DDC1B9 WDTEN SOAHDIS OSCHI FUNCTION HSync Polarity Select 0: Positive, 1: Negative VSync Polarity Select 0: Positive, 1: Negative H Dummy frequency Select 0 V Dummy frequency Select Bit 9 in DDC1 mode Enable Watch Dog Timer Disable SOA low to high detection OSC freq. Higher than 10 MHz
* CTRL3: Control Register 3 (Write Only) BIT 0 1 2 3 4 5-7 NAME ENHFO HDUMS1 HFO_POL HFO_HALF ENBNK1 FUNCTION Enable HF input/output for P4.0/P4.7, respectively 0: Disable, 1: Enable H Dummy frequency Select 1 Select HFO polarity 0: Positive, 1: Negative Select HFO output freq. 0: the same as HFI, 1: half of the HFI Select on-chip ext. RAM bank 0: Bank 0, 1: Bank 1 -
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Preliminary W78E378/W78C378/W78C374
*P1SF: Port1 special function output enable register (Write Only) BIT 0 1 2 3 4 5 6 7 NAME P10SF P11SF P12SF P13SF P14SF P15SF P16SF P17SF FUNCTION Port 1.0 Special Function enable (DAC0 output) Port 1.1 Special Function enable (DAC1 output) Port 1.2 Special Function enable (DAC2 output) Port 1.3 Special Function enable (DAC3 output) Port 1.4 Special Function enable (DAC4 output) Port 1.5 Special Function enable (DAC5 output) Port 1.6 Special Function enable (DAC6 output) Port 1.7 Special Function enable (DAC7 output)
*P2SF: Port2 special function output enable register (Write Only) BIT 0 1 2 3 4 5 6 7 NAME P20SF P21SF P22SF P23SF P24SF P25SF P26SF P27SF FUNCTION Port 2.0 Special Function enable (DAC8 output) Port 2.1 Special Function enable (DAC9 output) Port 2.2 Special Function enable (DAC10 output) Port 2.3 Special Function enable (Hclamp output) Port 2.4 Special Function enable (ADC0 input) Port 2.5 Special Function enable (ADC1 input) Port 2.6 Special Function enable (ADC2 input) Port 2.7 Special Function enable (ADC3 input)
*P3SF: Port3 special function output enable register (Write Only) BIT 0-2 3 4 5-7 NAME P33SF P34SF FUNCTION Port 3.3 Special Function enable (HOUT) Port 3.4 Special Function enable (VOUT) -
*HFCOUNTL: Horizontal frequency counter register, low byte (Read Only) BIT 0 1 2 3 4 5 6 7 NAME HF0 HF1 HF2 HF3 HF4 HF5 HF6 HF7 FUNCTION H frequency count bit 0 H frequency count bit 1 H frequency count bit 2 H frequency count bit 3 H frequency count bit 4 H frequency count bit 5 H frequency count bit 6 H frequency count bit 7
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
*HFCOUNTH: Horizontal frequency counter register, high byte (Read Only) BIT 0 1 2 3 4-5 6 7 NAME HF8 HF9 HF10 HF11 NOH HPOL FUNCTION H frequency count bit 8 H frequency count bit 9 H frequency count bit 10 H frequency count bit 11 Set by hardware if no Hin signal Hin polarity. 0: Positive, 1: Negative
*VFCOUNTL: Vertical frequency counter register, low byte (Read Only) BIT 0 1 2 3 4 5 6 7 NAME VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 FUNCTION V frequency count bit 0 V frequency count bit 1 V frequency count bit 2 V frequency count bit 3 V frequency count bit 4 V frequency count bit 5 V frequency count bit 6 V frequency count bit 7
*VFCOUNTH: Vertical frequency counter register, high byte (Read Only) BIT 0 1 2 3 4-5 6 7 NAME VF8 VF9 VF10 VF11 NOV VPOL FUNCTION V frequency count bit 8 V frequency count bit 9 V frequency count bit 10 V frequency count bit 11 Set by hardware if no VIN signal VIN polarity. 0: Positive, 1: Negative
* INTVECT: Interrupt Vector Register (Read Only) BIT 0 1 2 3 4 NAME SCLINT ADCINT DDC1INT SOAINT VEVENT FUNCTION SCL pin pulled low detected ADC conversion completed DDC1 port buffer empty SOA condition happen Vsync pulse detected or NOV = 1 (V counter overflow) (The VEVENT is designed to be generated only 'one' time if no Vsync input.) Parabola Interrupt generated
5
PARAINT
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Preliminary W78E378/W78C378/W78C374
* INTMSK: Interrupt Mask Register (Read/Write) BIT 0 1 2 3 4 5 NAME MSCLINT MADCINT MDDC1INT MSOAINT MVEVENT MPARAINT FUNCTION Set/clear to enable/disable SCLINT Set/clear to enable/disable ADCINT Set/clear to enable/disable DDC1INT Set/clear to enable/disable SOAINT Set/clear to enable/disable VEVENT Set/clear to enable/disable PARAINT
* INTCLR (Write Only) BIT 0 1 2 3 4 5 NAME CSCLINT CADCINT CDDC1INT CSOAINT CVEVENT CPARAINT FUNCTION Write 1 to this bit to clear SCLINT in INTVECT Write 1 to this bit to clear ADCINT in INTVECT Write 1 to this bit to clear DDC1INT in INTVECT Write 1 to this bit to clear SOAINT in INTVECT Write 1 to this bit to clear VEVENT in INTVECT Write 1 to this bit to clear PARAINT in INTVECT
*PARAL: Parabola interrupt generator register, low byte (Read/Write) BIT 0 1 2 3 4 5 6 7 NAME PARA0 PARA1 PARA2 PARA3 PARA4 PARA5 PARA6 PARA7 FUNCTION PARAINT period register bit 0 PARAINT period register bit 1 PARAINT period register bit 2 PARAINT period register bit 3 PARAINT period register bit 4 PARAINT period register bit 5 PARAINT period register bit 6 PARAINT period register bit 7
*PARAH: Parabola interrupt generator register, high byte (Read/Write) BIT 0 1 2 3 4 NAME PARA8 PARA9 PARA10 PARA11 PARA12 FUNCTION PARAINT period register bit 8 PARAINT period register bit 9 PARAINT period register bit 10 PARAINT period register bit 11 PARAINT period register bit 12
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
*SOARL: SOA register, low byte (Read/Write) BIT 0 1 2 3 4 5 6 7 NAME SL0 SL1 SL2 SL3 SL4 SL5 (OVL) (OVH) FUNCTION SOA Low register bit 0 SOA Low register bit 1 SOA Low register bit 2 SOA Low register bit 3 SOA Low register bit 4 SOA Low register bit 5 OVL = 1: current H count larger than SOARL, for test OVH = 1: current H count smaller than SOARH, for test
*SOARH: SOA register, high byte (Read/Write) BIT 0 1 2 3 4 5 6 7 * ADC * DAC0~DAC8 * DAC9~DAC10 * WDTCLR * SOACLR * DDC1 * S1CON * S1STA * S1DAT * S1ADR1, S1ADR2 * S2CON * S2STA * S2DAT * S2ADR1, S2ADR2 NAME SH0 SH1 SH2 SH3 SH4 SH5 (ADCSTRT) (WDTQ10) FUNCTION SOA High register bit 0 SOA High register bit 1 SOA High register bit 2 SOA High register bit 3 SOA High register bit 4 SOA High register bit 5 ADCSTRT bit status, for test Watch Dog Timer, bit 10, for test Result of the A-to-D conversion. 8-bit PWM static DAC register. 8-bit PWM dynamic DAC register. Watchdog-timer-clear register, without real hardware but an address. Writing any value to WDTCLR will clear the watchdog timer. Safe-Operation-Area Clear register, without real hardware but an address. Writing any value to SOACLR will clear the SOAINT. DDC1 latch buffer. SIO1 control register. SIO1 status register. SIO1 data register. SIO1 address registers. SIO2 control register. SIO2 status register. SIO2 data register. SIO2 address registers.
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Preliminary W78E378/W78C378/W78C374
Modified Timer 0 & Timer 1
Modified point in Timer 0 (Not divided by 12) OSC . .6
C/T = 0
To TL0 T0 pin (P3.5) TR0
C/T = 1
GATE INT0 pin (P3.2)
Modified point in Timer 1 (Not divided by 12) OSC . .6
C/T = 0
To TL1 T1 pin (P3.6) TR1
C/T = 1
GATE
VDD
Modified point in Timer 1 (No INT1 pin)
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
DDC1/SIO1 and SIO2 Ports 1. DDC1/SIO1 port
DDC Port SIO1
IN SCL OUT
SCL
IN SDA OUT
SDA
0
Support DDC2B/2B+
1
DDC1
SDA SCL
OUT Vsync
Support DDC1
ENDDC1
* ENDDC1 = 1, used as DDC1 (Display Data Channel) port:
To support DDC1, use Vsync signal for shift clock and P3.0 (SDA) for data output.
* ENDDC1 = 0, used as SIO1 port:
To support DDC2B/2B+/2Bi/2AB, use P3.1 (SCL) for serial clock and P3.0 (SDA) for serial data. SCLINT interrupt is generated when SCL (P3.1) has a high-to-low transition and then keeps at low for 16 x 1/Fosc. Fosc SCL low 2. SIO2 port: 8 MHz 2 S 10 MHz 1.6 S
* To support DDC2B/2B+/2Bi/2AB, use P4.4 (SCL) for serial clock and P4.5 (SDA) for serial data.
DDC1 Port The DDC1 is a serial output port that supports DDC1 communication. To enable the DDC1 port, ENDDC1 (bit 3 of CTRL1) should be set to '1'. Once previous eight data bits in the shift register and one null bit (the 9th bit) are shifted out to the SDA sequentially on each rising edge of the VIN signal, the DDC1 control circuit loads the next data byte from the latch buffer (the DDC1 register) to the shift register and generates a DDC1INT signal to the CPU. In the interrupt service routine, the S/W should fetch the next byte of EDID data and write it to the DDC1 register. If ENDDC1 is cleared, the shift register is stopped, and the SDA output is kept high. The bit DDC1B9 (bit 4 of CTRL2) decides the 9th bit in a DDC transmission. If DDC1B9 is set, the 9th bit will be '1', otherwise '0'.
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Preliminary W78E378/W78C378/W78C374
To use DDC1 port, a user should pay attention to the following items: (1) When the chip is powered-on or after reset , the 8-bit shift register in DDC1 H/W contains all 0s. If you write a data to the latch buffer (the DDC1 register), it will be loaded to the shift register at the 9th clock (on VIN), so from the 10th clock, the real data bit begins to shift out. (2) Because there is no reset signal to the latch buffer, it contains a random data after power-on. If you enable DDC1 without writing data to the latch buffer, SDA will have the random data shifted out after 9 clocks. The shift register is reset to 00H during CPU reset. (3) The DDC1 H/W has a counter that counts how many bits shifted out. This counter is initialized to 0 when power-up or reset. When you firstly enable DDC1 after power-on, the first bit is already shifted out without clock, so the first clock triggers the second data bit (D6) to shift out and "0000 0001 1" will be got. After the first 9 clocks that shift out an invalid byte, the counter counts from 1 to 9 cyclically according to the clock pulse on VIN-pin. See the following illustration. After power on, the counter count: shifted-out data bit: VIN clock pulse:
012345678 9 12 34 5 67 89 12 3 456 7 89 ...
000000001 1 12345678 9 |--> invalid data
D7 D6 D5 D4 D3 D2 D1 D0 ack 12 34 5 67 89
D7 D6 D5 D4 D3 D2 D1 D0 ack ... 12 3 456 7 89 ...
|--> normal data
(4) The interrupt happens on the failing edge of the following first clock. The next data, which is about to be shifted out, in the latch buffer is loaded into the shift register at the rising edge of the following first clock. At the same time, data bit D7 is shifted out and the counter value is "1". SIO1 Port (with two slave addresses) The SIO1 port is a serial I/O port, which supports all transfer modes from and to the I C bus. The SIO1 port handles byte transfers autonomously. To enable this port, the bit ENDDC1 in CTRL1 should be cleared to '0'. The CPU interfaces to the SIO1 port through the following five special function registers: S1CON (control register, D8h), S1STA (status register, D9h), S1DAT (data register, DAh) and S1ADR1/S1ADR2 (address registers, DBh/DCh). The SIO1 H/W interfaces to the 2 I C bus via two pins: SDA (P3.0, serial clock line) and SCL (P3.1, serial data line). The output latches of P3.0 and P3.1 must be set to "1" before using this port. SIO2 Port (with two slave addresses) The function of this port is the same as SIO1 port. The CPU interfaces to the SIO2 port through the following five special function registers: S2CON (control register, E8h), S2STA (status register, E9h), S2DAT (data register, EAh) and S2ADR1/S2ADR2 (address registers, EBh/ECh). The SIO2 H/W 2 interfaces to the I C bus via two pins: SDA2 (P4.5, serial clock line) and SCL2 (P4.4, serial data line). The output latches of P4.5 and P4.4 must be set to "1" before using this port. Operation of SIO1 Port: (SIO2 has the same function except their addresses of control registers)
2
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
a) Control Registers a-1) The Address Registers, S1ADR1, S1ADR2
The SIO1 is equipped with two address registers: S1ADR1 & S1ADR2. The CPU can read from and write to these two 8-bit, directly addressable SFRs. The content of these registers are irrelevant when SIO1 is in master modes. In the slave modes, the seven most significant bits must be loaded with the MCU's own address. The SIO1 hardware will react if either of the addresses is matched. 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 -
|------------------------ Own Slave Address -----------------------|
a-2) The Data Register, S1DAT
This register contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag (SI) is set. Data in S1DAT remains stable as long as SI is set. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. 7 SD7 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0
|<---------------------------- Shift direction ----------------------------S1DAT and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge bit into S1DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT on the falling edges of SCL clock pulses, and is shifted into S1DAT on the rising edges of SCL clock pulses.
a-3) The Control Register, S1CON
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the bus. The STO bit is also cleared when ENS1 = "0". 7 CR2 6 ENS1 5 STA 4 STO 3 SI 2 AA 1 CR1 0 CR0
ENS1, the SIO1 Enable Bit
ENS1 = "0": When ENS1 is "0", the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are ignored, SIO1 is in the not addressed slave state, and STO bit in S1CON is forced to "0". No other bits are affected. P3.0 (SDA) and P3.1 (SCL) may be used as open drain I/O ports. ENS1 = "1": When ENS1 is "1", SIO1 is enabled. The P3.0 and P3.1 port latches must be set to logic 1. - 18 -
Preliminary W78E378/W78C378/W78C374
STA, the START Flag
STA = "1": When the STA bit is set to enter a master mode, the SIO1 hardware checks the status of I2C bus and generates a START condition if the bus is free. If the bus is not free, then SIO1 waits for a STOP condition and generates a START condition after a delay. If STA is set while SIO1 is already in a master mode and one or more bytes are transmitted or received, SIO1 transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO1 is an addressed slave. STA = "0": When the STA bit is reset, no START condition or repeated START condition will be generated.
STO, the STOP Flag
STO = "0": When the STO bit is set while SIO1 is in a master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the SIO1 hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from an bus error condition. In this case, no STOP condition is transmitted to the I2C bus. However, the SIO1 hardware behaves as if a STOP condition has been received and switches to the defined not addressed slave receiver mode. The STO flag is automatically cleared by hardware. If the STA and STO bits are both set, then a STOP condition is transmitted to the I2C bus if SIO1 is in a master mode (in a slave mode, SIO1 generates an internal STOP condition which is not transmitted). SIO1 then transmits a START condition.
SI, the Serial Interrupt Flag
SI = "1": When a new SIO1 state is present in the S1STA register, the SI flag is set by hardware, and, if the EA and ES bits (in IE register) are both set, a serial interrupt is requested. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. When SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must be cleared by software. SI = "0": When the SI flag is reset, no serial interrupt is requested, and there is no stretching on the serial clock on the SCL line.
AA, the Assert Acknowledge Flag
AA = "1": If the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: 1) The own slave address has been received. 2) A data byte has been received while SIO1 is in the master receiver mode. 3) A data byte has been received while SIO1 is in the addressed slave receiver mode. AA = "0": If the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on SCL when: 1) A data has been received while SIO1 is in the master receiver mode. 2) A data byte has been received while SIO1 is in the addressed slave receiver mode.
CR0, CR1 and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency when SIO1 is in a master mode. It is not important when SIO1 is in a slave mode. In the slave modes, SIO1 will automatically synchronize with any clock frequency up to 100 KHz.
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Bit Freq. (KHz) @Fosc CR2 0 0 0 0 1 1 1 CR1 0 0 1 1 0 0 1 CR0 0 1 0 1 0 1 0 8 MHz 31.25 35.7 41.7 50.0 8.3 66.7 133.3 10 MHz 39.1 44.6 52.1 62.5 10.4 83.3 166.7 Fosc Divided By 256 224 192 160 960 120 60
a-4) The Status Register, S1STA
S1STA is an 8-bit read-only register. The three least significant bits are always 0. The five most significant bits contain the status code. There are 23 possible status codes. When S1STA contains F8H, no serial interrupt is requested. All other S1STA values correspond to defined SIO1 states. When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is present in S1STA one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit.
b) Operating Modes
The four operating modes are: Master/Transmitter, Master/Receiver, Slave/Transmitter and Slave/Receiver. Bits STA, STO and AA in S1CON decide the next action the SIO1 hardware will take after SI is cleared. When the next action is completed, a new status code in S1STA will be updated and SI will be set by hardware in the same time. Now, the interrupt service routine is entered (if the SI_interrupt is enabled), the new status code can be used to decide which appropriate service routine the software is to branch. Data transfers in each mode are shown in the following figures. *** Legend for the following four figures:
Last state Last action is done 08H A START has been transmitted. (STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; ACK bit will be received. 18H SLA+W has been transmitted; ACK has been received. Software's access to S1DAT with respect to "Expected next action": 1) "Data byte will be transmitted": Software should load the data byte (to be transmitted) into S1DAT before new S1CON setting is done. 2) "SLA+W (R) will be transmitted": Software should load the SLA+W/R (to be transmitted) into S1DAT before new S1CON setting is done. 3) "Data byte will be received": Software can read the received data byte from S1DAT while a new state is entered.
Next setting in S1CON Expected next action
New state Next action is done
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Preliminary W78E378/W78C378/W78C374
Master/Transmitter Mode
From Slave Mode (C) 08H
A START has been transmitted.
Set STA to generate a START.
(STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; ACK bit will be received.
From Master/Receiver (B) 18H
SLA+W has been transmitted; ACK has been received. or
20H
SLA+W has been transmitted; NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,0,X) Data byte will be transmitted; ACK will be received.
(STA,STO,SI,AA)=(1,0,0,X) A repeated START will be transmitted.
(STA,STO,SI,AA)=(0,1,0,X) A STOP will be transmitted; STO flag will be reset.
(STA,STO,SI,AA)=(1,1,0,X) A STOP followed by a START will be transmitted; STO flag will be reset.
28H
Data byte in S1DAT has been transmitted; ACK has been received. or
10H
A repeated START has been transmitted.
Send a STOP
Send a STOP followed by a START
30H
Data byte in S1DAT has been transmitted; NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,0,X) SLA+R will be transmitted; ACK bit will be received; SIO1 will be switched to MST/REC mode.
38H
Arbitration lost in SLA+R/W or Data bytes.
To Master/Receiver (A)
(STA,STO,SI,AA)=(0,0,0,X) I2C bus will be released; Not addressed SLV mode will be entered. (STA,STO,SI,AA)=(1,0,0,X) A START will be transmitted when the bus becomes free.
Enter NAslave
Send a START when bus becomes free
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Master/Receiver Mode
Set STA to generate a START.
From Slave Mode (C) 08H
A START has been transmitted.
(STA,STO,SI,AA)=(0,0,0,X) SLA+R will be transmitted; ACK will be received.
From Master/Transmitter (A)
48H
SLA+R has been transmitted; NOT ACK has been received.
40H
SLA+R has been transmitted; ACK has been received.
(STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned.
58H
Data byte has been received; NOT ACK has been returned.
50H
Data byte has been received; ACK has been returned.
(STA,STO,SI,AA)=(1,1,0,X) A STOP followed by a START will be transmitted; STO flag will be reset.
(STA,STO,SI,AA)=(0,1,0,X) A STOP will be transmitted; STO flag will be reset.
(STA,STO,SI,AA)=(1,0,0,X) A repeated START will be transmitted.
Send a STOP followed by a START
Send a STOP
10H
A repeated START has been transmitted.
38H
Arbitration lost in NOT ACK bit.
(STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; ACK will be received; SIO1 will be switched to MST/TRX mode.
(STA,STO,SI,AA)=(1,0,0,X) A START will be transmitted when the bus becomes free.
(STA,STO,SI,AA)=(0,0,0,X) I2C bus will be released; Not addressed SLV mode will be entered.
To Master/Transmitter (B)
Send a START when bus becomes free
Enter NAslave
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Preliminary W78E378/W78C378/W78C374
Slave/Transmitter Mode
Set AA
A8H
Own SLA+R has been received; ACK has been returned. or
B0H
Arbitration lost in SLA+R/W as master; Own SLA+R has been received; ACK has been returned.
(STA,STO,SI,AA)=(0,0,0,0) Last data byte will be transmitted; ACK will be received.
(STA,STO,SI,AA)=(0,0,0,1) Data byte will be transmitted; ACK will be received.
C8H
Last data byte in S1DAT has been transmitted; ACK has been received.
C0H
Data byte or Last data byte in S1DAT has been transmitted; NOT ACK has been received.
B8H
Data byte in S1DAT has been transmitted; ACK has been received.
(STA,STO,SI,AA)=(0,0,0,0) Last data byte will be transmitted; ACK will be received.
(STA,STO,SI,AA)=(0,0,0,1) Data byte will be transmitted; ACK will be received.
(STA,STO,SI,AA)=(1,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized; A START will be transmitted when the bus becomes free.
(STA,STO,SI,AA)=(1,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA; A START will be transmitted when the bus becomes free.
(STA,STO,SI,AA)=(0,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA.
Enter NAslave
Send a START when bus becomes free
To Master Mode (C)
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Slave/Receiver Mode
Set AA
60H
Own SLA+W has been received; ACK has been returned. or
68H
Arbitration lost in SLA+R/W as master; Own SLA+W has been received; ACK has been returned.
(STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned.
88H
Previously addressed with own SLA address; Data has been received; NOT ACK has been returned.
80H
Previously addressed with own SLA address; Data has been received; ACK has been returned.
A0H
A STOP or repeated START has been received while still addressed as SLV/REC.
(STA,STO,SI,AA)=(0,0,0,0) Data will be received; NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,0,1) Data will be received; ACK will be returned.
(STA,STO,SI,AA)=(1,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized; A START will be transmitted when the bus becomes free.
(STA,STO,SI,AA)=(1,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA; A START will be transmitted when the bus becomes free.
(STA,STO,SI,AA)=(0,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA.
Send a START when bus becomes free
Enter NAslave
To Master Mode (C)
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Preliminary W78E378/W78C378/W78C374
Parabola Interrupt Generator
The parabola interrupt generator is a 13-bit auto-reload timer, which generates an interrupt to the CPU periodically for software to load the parabola waveform data to the dynamic DACs (DAC8-DAC10). The software should calculate the value of the PARAH and PARAL registers by: (Vcount x 16) / segment number. The segment number is the number of integration segments between two Vsync pulses. The interrupt interval is programmable:
* Time base = 1/Fosc * Programmable interrupt period = Time base x (PARAH x 256 + PARAL + 1) * Maximum period = Time base x 8192
Note: Zero value in [PARAH, PARAL] is inhibited.
A-to-D Converter (ref. Application Note in Appendix A.) One 4-bit Analog-to-Digital Converter.
* Conversion time = (6/Fosc) x 128 sec. * 7 channels selected by an analog multiplexer
(ADCS2, ADCS1, ADCS0) (0, 0, 0) Selected Channel ADC0 (0, 0, 1) ADC1 (0, 1, 0) ADC2 (0, 1, 1) ADC3 (1, 0, 0) ADC4 (1, 0, 1) ADC5 (1, 1, 0) ADC6
The conversion of the ADC is started by setting bit ADCSTRT in CTRL1 by software. When the conversion is completed, the ADCSTRT bit is cleared by hardware automatically, and the ADCINT bit in INTVECT is set by hardware at the same time if MADCINT in INTMSK is set. PWM DACs Eight 8-bit Static DACs: DAC0-DAC7
* The PWM frequency FPWM = Fosc / 255 * The duty cycle of the PWM output = Register value / 255 * The DC voltage after the low pass filter = VCC x duty cycle
Static DAC application circuit:
Low-pass filter Static DAC R C V OUTPUT
T = RC VOUTPUT = V CCNn/255, if T >> T PWM
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Three 8-bit Dynamic DACs: DAC8-DAC10 The dynamic DACs are especially used to generate parabola waveform for geometric compensation, or to be used as static DACs. Dynamic DAC application circuit:
+Vsync
470 470 0.022u 470
100K
Dynamic DAC
10u/50V
VDD
10K 4.7u/16V 10K
Voutput
The following types of distoration can be compensated: 1. H size distortion: a. PinCushion Correction (Amplitude) b. Trapezoid (Keystone)
25%
c. CBOW (Quarter Width) d. PinCushion Correction (Corner) e. S Curve
25%
The PCC amplitude can be compensated against V size adjustment automatically. The Trapzoid can be compensated against V center adjustment automatically. 2. H center distortion: a. Pin balance (Bow) b. Key balance (Tilt) c. Corner balance
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Preliminary W78E378/W78C378/W78C374
Sync Processor
Polarity Detector The H/V polarity is detected automatically and can be known from HPOL bit (HFCOUNTH.7) and VPOL bit (VFCOUNTH.7). Fosc Max. H+V width Max. V width Sync Separator The Vsync is separated from the composite sync automatically, without any software effort. Fosc Min. V width & Max. H width 10 MHz (1/Fosc) x 64 = 6.4 S 10 MHz (64/Fosc) x 62 (counter overflow) = 396.8 S (2048/Fosc) x 2 = 409.6 S
Horizontal & Vertical Frequency Counter There are two 12-bit counters which can count H and V frequency automatically. When VEVENT (Vsync frequency counter timeout) interrupt happens, the count value values are latched into the counter registers (HFCOUNTH, HFCOUNTL, VFCOUNTH and VFCOUNTL). And then the S/W may read the count value (HCOUNT and VCOUNT) from the counter registers to calculate the H and V frequency by the formulas listed below. V frequency: The resolution of V frequency counter: VRESOL = (1/Fosc) x 64. The V frequency: VFREQ = 1/(VCOUNT x VRESOL). The lowest V frequency can be detected: Fosc / 262144. (38.1Hz @Fosc =10 MHz) H frequency: The resolution of H frequency counter: HRESOL = (1/Fosc) / 8. The H frequency: HFREQ = 1/(HCOUNT x HRESOL). The lowest H frequency can be detected: Fosc / 512. (19.5 KHz @Fosc = 10 MHz) Dummy Frequency Generator The Dummy H and V frequencies are generated for factory burn-in or showing warning message while there are no input frequency. (HDUMS1, HDUMS0) FdummyH Hsync width VDUMS FdummyV Vsync width (0, 0) Fosc/(8 x 4 x 8) (8 x 4)/Fosc 0 FdummyH/ 512 8/ FdummyH (0, 1) Fosc/(8 x 2 x 8) (8 x 2)/Fosc 1 FdummyH/1024 16/ FdummyH (1, 0) Fosc/(8 x 3 x 8) (8 x 3)/Fosc (1, 1) Fosc/(8 x 5 x 8) (8 x 5)/Fosc
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
1/FdummyH Hsync width
Hdummy Vdummy
Vsync width
..... .....
1/FdummyV
..... .....
..... .....
For Fosc = 10 MHz: (HDUMS1, HDUMS0) FdummyH Hsync width VDUMS FdummyV
0 152.6 Hz
(0, 1) 78.125 KHz 1.6 S
1 76.3 Hz 0
(1, 0) 52.083 KHz 2.4 S
1 50.9 Hz 0 101.7 Hz
(0, 0) 39.063 KHz 3.2 S
1 38.1 Hz 0 76.3 Hz
(1, 1) 31.250 KHz 4.0 S
1 30.5 Hz 61.0 Hz
H-clamp Pulse Generator 1. Leading edge/Trailing edge selectable. * HCES = 0: select leading edge * HCES = 1: select trailing edge
Negative polarity Hsync Hsync
Postive polarity Hsync Hsync
Hclamp
(Leading-edge)
Hclamp
(Leading-edge)
Hclamp
(Trailing-edge)
Hclamp
(Trailing-edge)
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Preliminary W78E378/W78C378/W78C374
2. Pulse width selectable. For Fosc = 10 MHz: HCWS = 0 Pulse Width 500-600 nS HCWS = 1 900-1000 nS
Safe Operation Area (SOA) Interrupt Upper boundary frequency = FOSC/ [8 x SOARH] Lower boundary frequency = FOSC/ [8 x (SOARL + 1)] Function description: * If the condition, HFREQ lower than the lower boundary freq. or higher than the upper boundary freq., happens twice continuously, the SOAINT will be activated. * If the HIN is stopped for a certain period, the SOAINT will also be generated. The no Hsync response time is 512/FOSC. (e.x., 51.2us for 10 MHz) * If SOAHDIS = 1, then no upper boundary frequency. Half Hsync Output When ENHFO (bit 0 of CTRL3) is set, P4.7 (HFO) will output the same or half frequency from P4.0 (HFI). The divide-by-two operation is done at the falling edge of HFI signal when HFO_HALF (bit 3 of CTRL3) is set. The polarity of HFO is specified by HF_POL (bit 2 of CTRL3).
HFI HFO (HFO_HALF=0) (HF_POL=1) HFO (HFO_HALF=0) (HF_POL=0) HFO (HFO_HALF=1)
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Interrupts
The five interrupt sources are listed as below. SOURCE VECTOR ADDRESS 1 2 3 4 5 IE0 TF0 IE1 TF1 SI1+SI2 0003H 000BH 0013H 001BH 002BH DESCRIPTON Interrupt 0 edge detected Timer 0 overflow Miscellaneous interrupts Timer 1 overflow SIO1 or SIO2 interrupt Lowest
*1
PRIORITY WITHIN A LEVEL Highest
Note: *1: SCLINT + ADCINT + DDC1INT + SOAINT + VEVENT + PARAINT.
The miscellaneous interrupts at vector address 0013H is driven by the following six sources, which are: (1) SCLINT: when high-to-low transition on SCL-pin, (2) ADCINT: when A-to-D conversion completion, (3) DDC1INT: when DDC1 data byte transmitted (after 9 clock pulses from VIN) in the DDC port, (4) SOAINT: when SOA activated, (5) VEVENT: on every Vsync pulse or vertical frequency counter overflow, (6) PARAINT: when parabola timer timeout. If IE1 interrupt occurs, it is necessary for the programmer to read the INTVECT register to tell where the interrupt request comes. These sources can be masked individually by clearing their corresponding bits in the INTMSK register. To clear any of these interrupt flags, just write a '1' to the corresponding bit in the INTCLR. The interrupt enable bits and priority control bits for these five main sources are listed as below. INTERRUPT FLAG 1 2 3 4 5 IE0 TF0 IE1 TF1 SI+SI2 ENABLE BIT IE.0 & IE.7 IE.1 & IE.7 IE.2 & IE.7 IE.3 & IE.7 IE.5 & IE.7 PRIORITY CONTROL BIT IP.0 IP.1 IP.2 IP.3 IP.5
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Preliminary W78E378/W78C378/W78C374
Vector Address IE0 TF0
IE 0003H 000BH
IE.0 IE.1
IP
IP.0 IP.1
High Priority Low Priority
Interrupt Polling Sequence IE1
0013H
IE.2 IP.2
TF1
001BH 002BH
IE.3
IP.3
SI1+SI2
IE.5 IE.7
IP.5
INTMSK
SCL Interrupt ADC Interrupt DDC1 Interrupt SOA Interrupt VEVENT Interrupt PARA Interrupt
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5
INTVECT
0 SCLINT 1 2 3 4 5
ADCINT DDC1INT SOAINT VEVENT PARAINT
0 IT1 1
IE1
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Reset Circuit- Power-low Detector & Watchdog Timer
The reset signals come from the following three sources: 1. External reset input (active low) 2. Power low detect 3. Hardware Watchdog Timer The power-low detection circuit generates a reset signal once the VCC falls below 3.5V for above 10 S or falls below 1.8V, and the reset signal is released after VCC goes up to 4.3V.
4.3V 3.8V 1.8V VCC Power-low Reset 10uS
The purpose of a watchdog timer is to reset the CPU if the user program fails to reload the watchdog timer within a reasonable period of time known as the "watchdog interval". The clock source of the watchdog timer comes from the internal system clock. It can be enabled/disabled by set/clear WDTEN (bit 5 of CTRL2). For debug purpose, if the WDT reset or power low reset occur, the RESET pin will be pulled low internally. The pulled-low duration due to WDT reset is about 60/Fosc sec. The block diagram of the reset circuitry is shown as below.
R:100K
/RESET
C:0.01u
Watchdog Timer
EN
Reset Logic
External Reset
WDTEN
Power-low Supervisor
Iol=12mA @Vol=0.45V
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Preliminary W78E378/W78C378/W78C374
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER DC Power Supply Input Voltage Input Current Operating Temperature Storage Temperature SYMBOL VDD VIN IIN TA
TST
MIN. -0.3 VSS -0.3 -100 0 -55
MAX. +7.0 VDD +0.3 +100 70 150
UNIT V V mA
C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
D.C. Characteristics
VDD-VSS= 5V 10%, TA = 25C, Fosc = 10 MHz, unless otherwise specified.
PARAMETER Operating Voltage Operating Current Power-down Current Input Input Current P2, P3.2-P3.4, P4.0 Input Current RESET Input Leakage Current P1, P2.4-P2.7(S.F. enabled) P3.0, P3.1, P3.5-P3.7, P4.4, P4.5 HIN, VIN Logical 1-to-0 Transition Current P2, P3.2-P3.4 Input Low Voltage P1, P2, P3 (except P3.0 & P3.1), P4.0, HIN, VIN, RESET , OSCIN
SYM. VDD IDD IPD IIN1 IIN2 ILK
SPECIFICATION MIN. 4.5 -75 -10 -300 -10 -10 TYP. 5 MAX. 5.5 30 100 -10 +10 -100 +10 +10
UNIT V mA A A A A
TEST CONDITIONS All function must pass! No load, VDD = 5.5V No load, VDD = 5.5V VDD = 5.5V, VIN = 0V VDD = 5.5V, VIN = 5.5V VDD = 5.5V, VIN = 0V VDD = 5.5V, VIN = 5.5V VDD = 5.5V, 0VITL
-650
-
-100
A
VDD = 5.5V, VIN = 2.0V
VIL1
0
-
0.8
V
VDD = 4.5V
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
D.C. Characteristics, continued
PARAMETER Input Low Voltage P3.0, P3.1, P4.4, P4.5 Input High Voltage P1, P2, P3 (except P3.0 &
P3.1), P4.0, HIN, VIN, RESET
SYM. VIL2 VIH1
SPECIFICATION MIN. 0 2.0 TYP. MAX. 0.3 VDD VDD +0.2
UNIT V V
TEST CONDITIONS VDD = 4.5V VDD = 5.5V
Input High Voltage P3.0, P3.1, P4.4, P4.5 Input High Voltage OSCIN Output Output Low Voltage P1.0, P1.1, RESET Output Low Voltage P3.0, P3.1, P4.4, P4.5 Output Low Voltage P1 (except P1.0 & P1.1) P2, P3 (except P3.0-P3.2) P4 (except P4.4 & P4.5) Output Low Voltage P3.2, OSCOUT Output High Voltage P2, P3.2-P3.4 Output High Voltage P4 (except P4.4 & P4.5) Special Function Output High Voltage P2.0-P2.3, P3.3, P3.4 Output High Voltage OSCOUT
Notes:
VIH2 VIH3
0.7 VDD 3.5
-
VDD +0.2 VDD +0.2
V V
VDD = 5.5V VDD = 5.5V
VOL1 VOL2 VOL3
-
-
0.45 0.45 0.45
V V V
VDD = 4.5V IOL = +12 mA VDD = 4.5V IOL = +8 mA VDD = 4.5V IOL = +4 mA
VOL4 VOH1 VOH2 VOH3
2.4 2.4 2.4
-
0.45 -
V V V V
VDD = 4.5V IOL = +0.8 mA VDD = 4.5V IOH = -100 A VDD = 4.5V IOH = -4 mA VDD = 4.5V IOH = -4 mA
VOH4
2.4
-
-
V
VDD = 4.5V IOH = -3 mA
*1. RESET has an internal pull-up resistor of about 30 K. *2. P2 and P3.2-P3.4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. *3. P3.0, P3.1, P4.4, P4.5, HIN, VIN and RESET are Schmitt trigger inputs.
- 34 -
Preliminary W78E378/W78C378/W78C374
Appendix A. Application Note for Usage of ADC
To use the ADC, users should pay attention to the following points: (1) According to the absolute maximum ratings, the input voltage should not exceed VDD +0.3V, especially for the ADC channel pins (P2.4-P2.7 & P3.5-P3.7). If a voltage over VDD +0.3V exists on any of these ADC channel pins, the AD conversion will fail. (2) Owing to the CMOS process, the ADC curve of some chip might differ from those of the others. So, before using the ADC, the S/W should do the ADC calibration described below. Step 1. Set (ADCS2, ADCS1, ADCS0, ADCcal) = (1, 1, 1, 0) and then do AD coversion to get the ADC value for the on-chip 0.948V input. Suppose it is A. Step 2. Set (ADCS2, ADCS1, ADCS0, ADCcal) = (1, 1, 1, 1) and then do AD coversion to get the ADC value for the on-chip 2.924V input. Suppose it is B. Step 3. Because the ADC curve in the usable range is linear, any V and X should meet the formula: (X-A)/(V-0.948) = (B-A)/(2.924-0.948), where V is the key voltage (designed by users and thus known) and X is its predicted ADC value. Then, we can get X = A + (V-0.948)(B-A)/(2.924-0.948), regardless of V > 0.948V or < 0.948V. (Of course, some effort should be paid in S/W to find X.) Step 4. Suppose there are N keys used, the N predicted ADC values for these keys can be found.
ADC value
B X Usable range (is linear) A
ADC input voltage 1.0 2.0 V 3.0 4.0 5.0
After finding these N predicted ADC values, the S/W can recognize which key is pressed by comparing the ADC value of this key with the set of predicted values (found previously).
** Note: To get the exact on-chip calibration voltages (0.948V and 2.924V), the VDD should be 5.0V as close as possible.
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Test strategy before shipping: (1) Vi = 0V => ADC < 20 (2) Vi = 0.8V => ADC > 25 (3) Vi = 3.2V => ADC < 248 (4) Vi = 4.4V => ADC = 255 (5) 0.8V < Vi < 3.2V, 25 points (step 0.1V) will be tested. All test points should be recognized correctly. Comment: a. (1) guarantees 0V input can be recognized (ADC value < 20). b. (4) guarantees 5V input can be recognized (ADC value = 255). c. (2), (3) and (5) guarantee linear (with 4 bits at least) within the usable range (0.8V to 3.2V).
25 20
ADC value
0.8 Usable range
248
3.2
4.4
Analog voltage (V)
- 36 -
Preliminary W78E378/W78C378/W78C374
PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in inches Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15 0.670 0.085 14.99 13.84 2.29 3.05 0 16.00 16.51 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 41.91 15.24 13.97 2.54 3.30 4.06 0.56 1.37 0.36 42.16 15.49 14.10 2.79 3.56 15 17.02 2.16 5.33
D
32 17
E1
A A1 A2 B B1 c D E E1 e1 L
a
1
16
eA S Notes:
E c
S
A A2
A1
Base Plane Seating Plane
L B B1
e1
a
eA
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches 6. General appearance spec. should be based on final visual inspection spec.
40-pin DIP
Symbol
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 14.986 0.550 0.110 0.140 15 0.670 0.090 13.72 2.286 3.048 0 16.00 16.51 0.254 3.81 0.406 1.219 0.203 3.937 0.457 1.27 0.254 52.20 15.24 13.84 2.54 3.302 4.064 0.559 1.372 0.356 52.58 15.494 13.97 2.794 3.556 15 17.01 2.286 5.334
D 40 21
E1
A A1 A2 B B1 c D E E1 e1 L
a
1 S
20 E c
eA S
Notes:
A A2
A1
Base Plane Seating Plane
L B B1
e1
a
eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
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Publication Release Date: December 1999 Revision A1
Preliminary W78E378/W78C378/W78C374
Package Dimensions, continued
44-pin PLCC
HD D
6 1 44 40
Dimension in inches
Dimension in mm
Symbol
7 39
Min.
0.020
E HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
Nom. Max. 0.185
Min.
0.51 3.68 0.66 0.41 0.20
Nom. Max. 4.70
3.81 0.71 0.46 0.25 3.94 0.81 0.56 0.36
0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014
0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 1.27 BSC 0.050 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 0.004 2.29 2.54 2.79 0.10
L A2 A
Seating Plane
e
b b1 GD
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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